As device dimensions continue to decrease in field-effect transistors (FETs), the gate channels between the source and drain regions of these transistors continue to get smaller. The dimensions have now shrunk to a point where short channel effects are creating significant problems for conventional planar FET designs. These short channel effects include a shift in the threshold voltage applied by the gate into the channel region to lower the current-flow barrier to electric charge flowing in the channel region between the source and drain region. Often, this shift in threshold voltage is caused by the voltage in the drain region of the transistor undesirably lowering the current-flow barrier in the channel region independently of the voltage applied by the gate. Another short channel effect is the degradation of the sub-threshold slope that defines the sensitivity of the threshold gate voltage to having the FET in an “on” or “off” position. Still another short channel effect is the greater amount of current flowing between the source and drain region when the FET is supposed to be in the “off” state. These short channel effects become increasingly problematic in planar FETs as the length of the channel region separating the source and drain regions of the transistor continues to decrease with each successive generation on the International Technology Roadmap for Semiconductors.
A further deleterious affect of shortening the channel region is the diminishment of the gate to act as an electrostatic control valve to prevent the leakage of charge from the source to the drain region. This diminishment is noticeably pronounced in planar FETs where the gate region contacts channel region along a single plane. As the channel region continues to shorten with successive generations of FETs, new designs that have the gate contacting the channel region along more than one plane have been developed. One of these designs forms the channel region has a raised strip of semiconductor material connecting the source and drain regions of the FET. The raised strip is colloquially referred to as a “fin”, and the device design is called a “finFET”. The raised fin channel permits the gate to surround and contact the channel along two or three planes, as opposed to the single plane of contact available to planar FETs.
Conventional methods of manufacturing finFETs include the deposition and etching of a dielectric material on a semi-conducting (e.g., silicon) substrate. For example, silicon oxide may be deposited on the substrate surface and then pattern etched to create trenches that are the molds for forming the fin channel regions of the finFETs. Unfortunately, the patterning of the dielectric material and the subsequent pre-cleaning that's typically necessary before depositing the fin material tend to overetch the sidewalls of the trenches, resulting in the fin being wider than desired. These overetching problems become more pronounced as the target width of the fin get smaller (e.g., 5-10 nm). At such small with dimensions, it is not uncommon for the overetching of the trench sidewalls to double the fin width.
Poor control of the etching and pre-clean operations can also result in a significant number of defects in the fin channel material. Because of the small dimensions of the fin channels, even a small number of dislocations, or even point defects, can significantly affect the channel region's ability to both stop and flow current between the source and drain regions of the finFET. Thus, there is a need for new methods of forming the fins of a finFET that provide more dimensional control and fewer defects in the fin. These and other challenges are addressed in the present Application.